1. Field of the Invention
The invention relates generally to the field of wireless communications, and more particularly to a voltage-controlled oscillator of a phase locked loop circuit.
2. Background of the Related Art
Phase Locked Loops (PLLs) have wide application in areas such as wireless communications systems and other products. In many applications, the PLL has very stringent performance requirements. There can be more than one PLL circuit 110, 120 in a typical wireless system. For example, a typical block diagram of a receiver using a super-heterodyne architecture 100 is shown in FIG. 1. Those skilled in the art will readily recognize the various blocks and their functions, so a detailed recitation of the block diagram will not be further described herein.
PLLs used in wireless communication systems provide a highly stable carrier signal for the modulation and the demodulation processes. The carrier signal should have sufficient spectral purity (often represented as phase noise characteristics of the voltage-controlled oscillator (VCO) in the PLL) and support the required channel spacing in the desired band. For example, Korean cellular phone standards include the IS-95 Standard For Code Division Multiple Access (CDMA) digital service at around 900 MHz and 1700 MHz. European cellular phone standards include the Global System For Mobile Communications (GSM) operating in the 900 MHz band and Defense Communications System (DCS) in the 1800 MHz range. Although the occupied frequency band is similar, the required channel spacing for the PLL differs according to the particular standard. For example, IS-95 standard requires 1.25 MHz channel spacing with a 10 KHz channel raster. On the other hand, GSM and DCS standards require 200 KHz channel spacing in the allocated frequency bands. Since the PLL in the wireless communication transceiver generates the appropriate very high frequency (VHF) signal with high accuracy, the PLL can use a highly stable Voltage-controlled Temperature Compensated Crystal Oscillator (VCTXO) as the reference clock.
FIG. 2 shows a generic block diagram of a PLL commonly used in wireless communication equipment. As shown therein, the PLL includes a reference divider 202, a feedback divider 210, a voltage-controlled oscillator (VCO) 208, a phase frequency detector (PFD) 204, a charge pump circuit (not shown) and a loop filter (LF) 206. The PFD 204 compares the phase of the divided reference clock signal and the divided output of the VCO 208. Depending upon the magnitude and polarity of the phase error, the charge pump circuit generates UP or DOWN signals at its output, where the width of the pulses are proportional to the detected phase error. The charge pump circuit generates an amount of the charge equivalent to the error signal. The net charge is accumulated at the LF 206, which serves as a control signal of the VCO 208. A simple form of the LF 206 is a series combination of a resistor and a capacitor (i.e., a first order filter). However, in modern PLL design, higher order loop filters can be used to get better performance in phase noise and spurious response. The resulting voltage from LF 206 is connected to a frequency control terminal of the VCO 208. Due to the negative feedback loop, the PLL of FIG. 2 achieves a stable output frequency. The stable output frequency situation will exist when the net change of the loop filter 206 voltage becomes zero. At this point, the frequency and the phase of the VCO 208 do not change, on average. In this locked state, the frequency of the VCO 208 is simply expressed as follows.                               f          vco                =                              L            N                    ⁢                      f            REF                                              (        1        )            Where ƒvco=the VCO frequency, L=the feedback divider, N=the reference divider, and ƒref=the reference frequency. In the above equation (1), the coefficient of the feedback divider can be integer, but also can contain some fractional part in some applications.
There are numerous factors in designing PLL circuits for specific applications. The common factors are circuit area, cost, and power consumption. Performance characteristics such as lock time and phase noise depend on the system in which the PLL is used. According to the system requirements, design parameters such as division factors, loop bandwidth, and circuit design are affected. For example, in GSM applications, 200 KHz channel spacing with 13 MHz reference frequency is required, with a lock time of several msec. Thus, an integer-N frequency synthesizer and normal loop bandwidth can be used to meet the requirement. However, in General Packet Radio Service (GPRS) applications, the generic integer-N frequency synthesizer cannot be used, because a lock time of less than 150 μs is required. In this case, fractional-N synthesizer or sigma-delta based synthesizers are commonly used.
In other applications, required frequency resolution in the PLL is 10 KHz, even though the channel spacing is 1.25 MHz. There are several reasons for this. First, the most common reference frequency in IS-95 applications is 19.2 MHz, which is not a multiple of 1.25 MHz. Second, the required frequency resolution depends on the choice of the Intermediate Frequency (IF) signal when the PLL is used in a super-heterodyne transceiver. Where the common IF frequency is 85.38 MHz in the receiving mode, the frequency resolution should be 10 KHz in the local oscillator. Third, compatibility with old standards such as Advanced Mobile Phone Service (AMPS) requires the frequency resolution of 10 KHz in generating the local oscillator (LO) signal.
The performance of the related art PLL is limited by that of the VCO 208, and important characteristics of the VCO 208 include the phase noise performance. The remaining components such as the PFD 204 and frequency dividers 202 and 210 also contribute to the overall noise performance of the PLL output. Phase noise is usually defined as the ratio of the carrier power to the sideband power in 1 Hz at the specific offset frequency from the carrier. Phase noise has the unit of dBc/Hz. The VCO 208 is a sensitive device, and its phase noise performance characteristic may be greatly affected by environmental conditions such as power supply variation, temperature and noise. A factor representing the sensitivity of the VCO 208 is its gain, usually expressed as Kvco (MHz/V). For low-noise PLL applications, the VCO 208 can have a relatively low gain, thus low sensitivity. The low gain of the VCO 208 reduces the effect of the external noise by minimizing the AM-to-FM modulation.
Since the phase noise specification in mobile phone applications is so stringent, the allowable types of the VCO are limited, and an LC oscillator is usually used. The LC oscillator consists of a resonant tank circuit and a few active devices to compensate the energy loss in the tank circuit. Since the tank circuit is a type of band-pass filter, the phase noise performance of the LC oscillator is better than other types of oscillators. The nominal frequency of the LC oscillator is expressed as follows.                               f          vco                =                  1                      2            ⁢            π            ⁢                          LC                                                          (        2        )            In equation 2, ƒvco=the nominal frequency of the VCO, L=the inductance, and C=the capacitance. There are two possibilities for controlling the frequency of the VCO. However, since the formation of a variable inductor is not easy, a variable capacitor can be used for controlling the frequency of the VCO.
It was common to design the VCO with a discrete tank circuit, some passive components and active devices. But this approach leads to large circuit area and high cost. There is a recent trend that drives those functional blocks into the monolithic form. The most difficult factor in the design of a fully integrated LC oscillator is to guarantee stable operation against process and environmental variations. The variation of a capacitor or inductor grown above silicon exceeds 10% in a worst case. Referring to equation (2), it is seen that the percentage of change in the operating frequency also becomes 10% in that case. Thus, the total operating range of the VCO should cover this frequency shift as well as the desired frequency range. However, the wide tuning range conflicts with the design goal of small gain in order to achieve low phase noise characteristics.
The above-described trade-off between the low phase noise and the wide tuning range has been solved with various discrete tuning methods. FIG. 3 shows a schematic of a VCO according to the related art. The resonant LC circuit 310 controls the frequency of the oscillator 300. LC circuit 310 includes a capacitor 312, inductor 314, varactor diodes 316 and 320, and switches 318. In operation, when a lock is not achieved in the PLL, the varactor diodes 316 are selectively switched to control the frequency of the VCO. When the operating frequency of the VCO is faster than the desired frequency, more switches are closed to reduce the operating frequency of the VCO, and vice versa. In the related art circuit of FIG. 3, the value of capacitor 312 is of little significance because of the capacitance of varactor diodes 316 and 320.
The LC circuits of related art VCO's have various disadvantages. For example, referring to FIG. 3, there is no DC current path in the off-state of switch 318. Thus, a bias level of a floated terminal of a corresponding diode 316 is unknown and very sensitive to the leakage. When an initial bias condition of such a floated terminal is too high or low, it can greatly affect the device reliability.
FIGS. 4, 5A, and 5B show similar related art VCO's, except in a differential implementation, and where an equivalent capacitor has been substituted for each varactor diode. As shown in FIG. 4, all switches except SW(1) and SWB(1) are closed, and thus our concern is focused on the behavior of the floated nodes NSC(1) and NSCB(1). Where the initial bias voltage of the floated terminal is assumed to be same as the common mode voltage of the oscillator, the waveform of the floated terminal is almost same as the waveform of the oscillator output, and little or no degradation in performance is presented.
However, FIG. 5A illustrates the case in which some amount of the positive charge is stored in the capacitor plate connected to NSC(1) just after disconnection of the switch SW(1), and where some amount of the negative charge is stored at the other plate of capacitor SCB(1). Because there is no DC current path during the off-state, there is a positive offset voltage between the NSC(1) node and the OUT node. Where the offset voltage is excessive, the switches may be damaged, and the reliability of the VCO may be degraded.
FIG. 5B illustrates another undesirable situation. When an NMOS switch is used to control the switchable capacitor, the drain junction can be forward-biased. Since this kind of parasitic junction has a very poor quality factor, the phase noise performance in this case will be severely degraded.
Other problems and disadvantages also exist as will be appreciated by those skilled in the art. U.S. Pat. Nos. 6,137,372 and 5,739,730 are examples of related art systems.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.